FIG. 3 illustrates an example of a domino logic circuit, which is one example of a dynamic logic circuit. A domino logic circuit of this kind is described in the publication "Principles of CMOS VLSI Design", by Neil H. E. Weste and Kamran Eshraghian, inspected/translated by Takashi Tomizawa and Yasuo Matsuyama, Maruzen K. K. , pp. 142-144, by way of example.
The domino logic circuit of FIG. 3 has a logical evaluation unit 90 which includes a logic network 92 composed of a plurality of nMOS transistors in serial/parallel connection. A pMOS transistor P92 for precharging is disposed between the logic network 92 and a power supply terminal and a precharge signal PCH is applied to the pMOS transistor P92 as a gate input. The point at which the logic network 92 and precharge pMOS transistor P92 are connected serves as a precharge node PC90. An nMOS transistor N94 for permitting evaluation is disposed between the logic network 92 and a ground terminal, and the precharge signal PCH is applied to the nMOS transistor P94 as a gate input. A leakage compensation circuit 93 comprising an inverter INV1 and a pMOS transistor P91 is connected to the precharge node PC90.
A pMOS transistor P90 making up an output buffer 91 is disposed between an output terminal OUT0 and a power supply terminal, an nMOS transistor N90 making up this output buffer 91 is disposed between the output terminal OUT0 and a ground terminal, and the precharge node PC90 is connected to the gate inputs of these transistors.
In the following, specific analysis is given by the present inventors for illustrating the problems encountered in the prior art.
In the operation of the domino logic circuit shown in FIG. 3, assume first that the precharge signal PCH is at the low level. In this case the domino logic circuit operates in a precharge cycle. During the precharge cycle, the pMOS transistor P92 for precharging is conductive and the precharge node PC90 is charged. On the other hand, the nMOS transistor N94 for permitting evaluation is rendered non-conductive and the connection between the precharge node PC90 and the ground terminal is severed regardless of the states of input terminals IN0, . . . INx of the logic network 92.
Since the precharge node PC90 is charged and assumes the high level, the pMOS and nMOS transistors P90, N90 of the buffer 91 are rendered non-conductive and conductive, respectively. The output terminal, therefore, discharges.
If the precharge signal PCH is at the high level, the domino logic circuit operates in an evaluation cycle. During the evaluation cycle, the precharge pMOS transistor P92 is non-conductive and the evaluation n-MOS transistor N94 is conductive. The precharge node PC90 is discharged via the evaluation-permitting nMOS transistor N94 only if the result of evaluating the logic by the logic network 92 is true. Furthermore, the input to the pMOS transistor P90 of the buffer also is discharged and reverts to the low level, the pMOS transistor P90 and the nMOS transistor N90 of the buffer are rendered conductive and nonconductive, respectively, and the potential at the output terminal rises to the high level.
If the result of evaluation by the logic network 92 is false, the precharge node PC90 is not discharged and no change in the potential of the output terminal occurs. In this case the input potential of the buffer transistors P90 and N90 is fixed at the high level by the electric charge that has been accumulated in the precharge node PC90.
In an ordinary static logic circuit, the output potential of the circuit is decided by the power supply potential delivered via a transistor that has been rendered conductive. Even if noise occurs, therefore, the output potential always recovers to the power supply potential.
By contrast, if the result of evaluation by the logic network in a dynamic logic circuit such as the domino logic circuit is false, the result is a floating state in which the dynamic node is not connected to either the power supply or ground. This causes a major decline in tolerance to noise.
In order to compensate for this problem, the general practice is to add on a leakage compensation circuit which compensates for leakage caused by noise.
In the domino logic circuit shown in FIG. 3, the leakage compensation circuit 93 is added onto the dynamic node PC90. The leakage compensation circuit 93 drives the leakage pMOS transistor P91 by the inverter INV1, the input to which is the dynamic node PC90, thereby compensating for noise-induced leakage.
Of the MOS transistors constructing the inverter (buffer) 91 of the output stage in the prior-art domino logic circuit described above, the transistor that operates in the evaluation cycle is solely the pMOS transistor that discharges the output terminal. The nMOS transistor appears only as a load during the evaluation cycle. This is the cause of a delay.
A technique for speeding up a dynamic logic circuit is disclosed for example in the specification of Japanese Patent Application Laid-Open (KOKAI) No. 8-84066 entitled "Dynamic Logic Circuit". Specifically, this application proposes a dynamic-type logic circuit in which a single logic module is constructed by directly connecting the output terminals of a plurality of dynamic logic gates, which comprise a logical operation network constructed by combining a plurality of semiconductor switches, a precharge semiconductor switch connected between the logical operation network and a power supply terminal and a discharging semiconductor switch connected between the logical operation network and a ground terminal, to the input terminals of a static logic gate comprising a logical operation network constructed by combining a plurality of complementary semiconductor switches. FIG. 4 illustrates an example of the dynamic logic circuit proposed by the aforesaid Japanese Patent Application Laid-Open No. 8-84066.
As shown in FIG. 4, the logic circuit is composed primarily of three sections. NOR gates 81 and 82 construct OR logic using ordinary domino logic circuits. Inverter sections added onto the outputs from these domino logic circuits are deleted. Accordingly, the internal dynamic nodes are connected directly to respective output terminals PC81 and PC82. The output terminals PC81 and PC82 of the two dynamic logic circuits NOR 81 and NOR 82 are connected to the inputs of a NOR gate 83. The NOR gate 83 is an ordinary CMOS static logic circuit. In addition to implementing a NOR function, the NOR gate 83 acts as the buffer of the outputs from the two dynamic logic circuits NOR 81, and NOR 82.
The operation of the prior-art dynamic logic circuit shown in FIG. 4 will now be described.
The basic operation of the two dynamic logic circuits NOR 81 and NOR 82 is substantially the same as that of the domino logic circuit described above with reference to FIG. 3. In the precharge cycle, the precharge transistors are rendered conductive and the respective precharge nodes are charged. On the other hand, the transistors for permitting evaluation (i.e., the discharging transistors) are rendered non-conductive to prohibit the discharge of the precharge nodes.
In the evaluation cycle, the precharge transistors become non-conductive and the evaluation-permitting transistors become conductive. The logic is evaluated by the logic networks constructed by nMOS transistors (namely by the NOR logic constructed by two parallel-connected nMOS transistors MN1, MN2 or by two parallel-connected nMOS transistors MN4, MN5). If the logic is true, the precharge nodes PC81, PC82 are discharged. If the logic is false, the precharge nodes PC81, PC82 are held in the floating state. In order to compensate for deteriorated tolerance to noise when the floating state prevails, a leakage compensation circuit comprising an inverter INV1 and a pMOS transistor MP2 is added onto the precharge node PC81, and a leakage compensation circuit comprising an inverter INV2 and a pMOS transistor MP4 is added onto the precharge node PC82.
The precharge nodes PC81, PC82 of the respective NOR gates 81, 82 are connected to the inputs of the static logic circuit NOR 83. The latter is an ordinary CMOS logic circuit, which evaluates logic based upon its inputs and generates an output potential. What generates the input signals are the dynamic logic circuits. This assures that the transition from the high to low level will occur only once in the evaluation cycle. In the static logic circuit NOR 83 disposed as the succeeding stage, therefore, only pull-down nMOS transistors MN7, MN8, the respective gate inputs of which are the precharge nodes PC81, PC82, operate to perform discharge at the output terminal when the precharge cycle prevails. Only pull-up pMOS transistors MP5, MP6 operate to perform charging at the output terminal when the evaluation cycle is in effect.
In the precharge cycle, generally there is some margin in terms of delay since it will suffice if the discharging of the output terminal and the charging of the precharge nodes is carried out in this cycle. In view of this property, it is recommended that the sizes of the nMOS transistors on the pull-down side in the dynamic logic circuit of FIG. 4 be made smaller than the sizes of the pMOS transistors on the pull-up side.
By adopting the circuit arrangement in which the dynamic logic circuits are placed in the preceding stage and the static logic circuit is placed in the preceding stage, it is possible to shorten the signal delay ascribable to the inverter added onto the output, this being the problem peculiar to the domino logic circuit, a high-speed circuit can be realized as a result. Eliminating the inverter is effective also is reducing the area of the device. Furthermore, with the domino logic circuit, all logic is constructed of dynamic logic circuits, meaning that power consumption is large. With the logic circuit shown in FIG. 4, however, using the static logic circuit in part of the device reduces the power consumed.
In a case where OR logic is employed as the static logic circuit as the succeeding stage of this conventional dynamic logic circuit, however, the fact that the pMOS transistors are serially connected means that the load capacitance driving capability is inferior in comparison with the case where the inverter is used as the succeeding stage of the simple domino logic circuit.
In case of the above-mentioned logic circuit which obtains an output signal by driving the inverter of the succeeding stage by the nMOS logic network of the preceding stage, a problem which arises is an increase in the delay time of the entire circuit owing to the signal delay in the inverter, as set forth above.
The reason for this problem is as follows: Of the nMOS transistor and pMOS transistor constructing the inverter of the succeeding stage, the transistor that operates in the evaluation cycle is solely the pMOS transistor; the nMOS transistor is driven by the nMOS logic network, the driving capability of which is exceedingly poor. The result is an increase in delay time.
In a case where OR logic is employed as the static logic circuit as the succeeding stage in the conventional dynamic logic circuit described above in connection with FIG. 4, the fact that the pMOS transistors are serially connected means that the load capacitance driving capability is inferior to the case where the inverter is used as the succeeding stage of the simple domino logic circuit.